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Optional: Create a custom component library, and disable the VHDL defaults. Alternatively, the VHDL defaults may be edited. The component definitions form a critical part of the assumptions made when evaluating a device, and should be carefully documented.

By default, the component definitions imported from the VHDL will have a set of operating modes which describe connectivity that seems reasonable given the declarations in the VHDL. For each component, a default normal mode is provided, and a default faulty mode. These connect the ports according to the following table:

VHDL Port mode		SIFA Operating mode
from	to
in	in	default-fault
in	out	default-normal
in	inout	default-normal
out	in
out	out
out	inout
inout	in	default-fault
inout	out	default-normal
inout	inout	default-normal

As such, the component CMP from the running example:

component CMP
    port
    (
        p1,p2 : in STD_LOGIC;
        p3,p4 : out STD_LOGIC
    );
end component;

Has been given the following definition by default (this is from the Modes tab in the CMP view):

[COMPONENT: CMP]	p1	p2	p3	p4
p1	default-normal default-fault	default-fault	default-normal	default-normal
p2	default-fault	default-normal default-fault	default-normal	default-normal
p3			default-normal default-fault
p4				default-normal default-fault

However, this is not how we want the component to behave, so we edit the modes to take on the following form:

This can either be done in-situ, or the CMP component definition disabled, and a new one created elsewhere. Creating the definition elsewhere can help in recycling component definitions for future projects.

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